Reduced Order Long Interconnect Modeling

As the size of the integrated circuits become smaller with higher speed of operation, the RLC interconnect effects have greater impact on signal propagation and signal integrity issue that is reflected in terms of noise or cross talk effects and giving rise to delay, ringing, glitches and overshoot, undershoot or false signaling problems etc. (figure-1, [7]). These definitely impose a great challenge to the high speed IC designer. There are several traditional distributed models of interconnect based on Elmore delay [3] available in the literature. Unfortunately, most of them (e.g., [1][2]) are only based on the resistance and capacitance and obviously are not suitable enough to model the behaviour of long interconnects in high frequency operation. However, since inductance effects in on-chip interconnects have become increasingly important in high frequency operation, an accurate equivalent circuit based on RLC components for modelling the high frequency behaviour of two or more parallel interconnect lines is necessary. Furthermore, as stated in [2], in general, the impedance conditions (i.e., source impedance Rs, the line resistance Rline, and load impedance, ZL ) have a substantial influence on the crosstalk noise. More specifically, as per [2] if Rline > 2.Rs , the inductance effect can be neglected with 10% error. However, if Rs >> Rline , and Rline >> ZL , the inductive coupling noise can not be neglected and may become significant. Fortunately, for practical CMOS circuits this may not be case where the driver resistance is moderate and the receiver is high impedance capacitive load. Thus for the CMOS circuits, composed of CMOS inverter driver, interconnect and inverter receiver, can be modelled neglecting the inductive coupling noise. Therefore, in this paper an attempt has been made to model efficiently such interconnect line so that the reduced order (simple) model is sufficient enough for good circuit simulation with minimum loss of accuracy.